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1 for more information www.linear.com/ltc4365 typical a pplica t ion fea t ures descrip t ion overvoltage, undervoltage and reverse supply protection controller 12v automotive application a pplica t ions n wide operating voltage range: 2.5v to 34v n overvoltage protection to 60v n reverse supply protection to C40v n ltc4365: blocks 50hz and 60hz ac power n ltc4365-1: fast (1ms) recovery from fault n no input capacitor or tvs required for most applications n adjustable undervoltage and overvoltage protection range n charge pump enhances external n-channel mosfet n low operating current: 125a n low shutdown current: 10a n compact 8-lead, 3mm 2mm dfn and tsot-23 (thinsot?) packages n portable instrumentation n industrial automation n laptops n automotive surge protection l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and thinsot and hot swap are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. load protected from reverse and overvoltage at v in the lt c ? 4365 protects applications where power supply input voltages may be too high, too low or even negative. it does this by controlling the gate voltages of a pair of external n-channel mosfets to ensure that the output stays within a safe operating range.the ltc4365 can withstand voltages between C40 v and 60 v and has an operating range of 2.5 v to 34 v, while consuming only 125a in normal operation. tw o comparator inputs allow configuration of the over - voltage ( ov) and undervoltage ( uv) set points using an external resistive divider. a shutdown pin provides external control for enabling and disabling the mosfets as well as placing the device in a low current shutdown state . a fault output provides status of the gate pin pulling low. a fault is indicated when the part is in shutdown or the input voltage is outside the uv and ov set points. the ltc4365 has a 36 ms turn-on delay that debounces live connections and blocks 50 hz to 60 hz ac power. for fast recovery after faults, the ltc4365-1 has a reduced 1ms turn-on delay. ?30v gnd 10v/div 30v 4365 ta01b 1s/div uv = 3.5v ov = 18v v out v out v in v in valid window v in uv ov shdn ov = 18v uv = 3.5v 4365 ta01a v out fault gate v in 12v v out 3a si4946 gnd ltc4365 510k 1820k 243k 59k ltc 4365 4365fa
2 for more information www.linear.com/ltc4365 p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltage ( note 1) v in .......................................................... C40 v to 60 v input voltages ( note 3) uv , shdn .............................................. C 0.3 v to 60 v ov ............................................................ C 0.3 v to 6v v out ....................................................... C0.3 v to 40 v output voltages ( note 4) fa u lt ..................................................... C 0.3 v to 60 v gat e ....................................................... C40 v to 45 v top view 9 gnd ddb package 8-lead (3mm 2mm) plastic dfn 5 6 7 8 4 3 2 1gnd ov uv v in shdn fault v out gate t jmax = 150c, ja = 76c/w exposed pad ( pin 9) pcb ground connection op tional 1 2 3 4 8 7 6 5 top view ts8 package 8-lead plastic tsot-23 gate v out fault shdn v in uv ov gnd t jmax = 150c, ja = 195c/w input currents uv , ov , shdn .................................................... C1 ma op erating ambient temperature range ltc 43 65 c ................................................ 0 c to 70 c ltc 43 65 i ............................................. C 40 c to 85 c ltc 43 65 h .......................................... C4 0 c to 125 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) for tsot only ................................................... 30 0 c ltc 4365 4365fa
3 for more information www.linear.com/ltc4365 lead free finish tape and reel (mini) tape and reel part marking* package description temperature range ltc4365cddb#trmpbf ltc4365cddb#trpbf lfks 8-lead (3mm 2mm) plastic dfn 0c to 70c ltc4365cddb-1#trmpbf ltc4365cddb-1#trpbf lgmb 8-lead (3mm 2mm) plastic dfn 0c to 70c ltc4365iddb#trmpbf ltc4365iddb#trpbf lfks 8-lead (3mm 2mm) plastic dfn C40c to 85c ltc4365iddb-1#trmpbf ltc4365iddb-1#trpbf lgmb 8-lead (3mm 2mm) plastic dfn C40c to 85c ltc4365hddb#trmpbf ltc4365hddb#trpbf lfks 8-lead (3mm 2mm) plastic dfn C40c to 125c ltc4365hddb-1#trmpbf ltc4365hddb-1#trpbf lgmb 8-lead (3mm 2mm) plastic dfn C40c to 125c ltc4365cts8#trmpbf ltc4365cts8#trpbf ltfkt 8-lead plastic tsot-23 0c to 70c ltc4365cts8-1#trmpbf ltc4365cts8-1#trpbf ltgkz 8-lead plastic tsot-23 0c to 70c ltc4365its8#trmpbf ltc4365its8#trpbf ltfkt 8-lead plastic tsot-23 C40c to 85c ltc4365its8-1#trmpbf ltc4365its8-1#trpbf ltgkz 8-lead plastic tsot-23 C40c to 85c ltc4365hts8#trmpbf ltc4365hts8#trpbf ltfkt 8-lead plastic tsot-23 C40c to 125c ltc4365hts8-1#trmpbf ltc4365hts8-1#trpbf ltgkz 8-lead plastic tsot-23 C40c to 125c trm = 500 pieces. *temperature grades are identified by a label on the shipping container. consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v in , v out v in input voltage range operating range protection range l l 2.5 C40 34 60 v v i vin input supply current shdn = 0v, v in = v out , C40c to 85c shdn = 0v, v in = v out , C40c to 125c shdn = 2.5v l l l 10 10 25 50 100 150 a a a i vin(r) reverse input supply current v in = C40v, v out = 0v l C1.2 C1.8 ma v in(uvlo) input supply undervoltage lockout v in rising l 1.8 2.2 2.4 v i vout v out input current shdn = 0v, v in = v out shdn = 2.5v, v in = v out v in = C40v, v out = 0v l l l 6 100 20 30 250 50 a a a gate v gate n-channel gate drive (gate-v out ) v in = v out = 5.0v, i gate = C1a v in = v out = 12v to 34v, i gate = C1a l l 3 7.4 3.6 8.4 4.2 9.8 v v i gate(up) n-channel gate pull up current gate = v in = v out = 12v l C12 C20 C30 a i gate(fast) n- channel gate fast pull down current fast shutdown, gate = 20v , v in = v out = 12v l 31 50 72 ma i gate ( slow) n-channel gate gentle pull down current gentle shutdown, gate = 20v , v in = v out = 12v l 50 90 150 a t gate(fast) n-channel gate fast turn off delay c gate = 2.2nf, uv or ov fault l 2 4 s t gate ( slow) n-channel gentle turn off delay c gate = 2.2nf, shdn falling, v in = v out = 12v l 150 250 350 s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 2.5v to 34v, unless otherwise noted. (note 2) o r d er i n f or m a t ion ltc 4365 4365fa
4 for more information www.linear.com/ltc4365 symbol parameter conditions min typ max units t recovery gate recovery delay time v in = 12v, power good to v gate > 0v ltc4365, c gate = 2.2nf ltc4365-1, c gate = 2.2nf l l 26 0.6 36 1 49 1.5 ms ms uv , ov v uv uv input threshold voltage uv falling v gate = 0v l 492.5 500 507.5 mv v ov ov input threshold voltage ov rising v gate = 0v l 492.5 500 507.5 mv v uvhyst uv input hysteresis l 20 25 32 mv v ovhyst ov input hysteresis l 20 25 32 mv i leak uv, ov leakage current v = 0.5v, v in = 34v l 10 na t fault uv, ov fault propagation delay overdrive = 50mv v in = v out = 12v l 1 2 s shdn v shdn shdn input threshold shdn falling to v gate = 0v l 0.4 0.75 1.2 v i shdn shdn input current shdn = 0.75v, v in = 34v l 10 na t start delay coming out of shutdown mode shdn rising to v gate > 0v , v in = v out = 12v l 400 800 1200 s t shdn(f) shdn to fault asserted v in = v out = 12v l 1.5 3 s t lowpwr delay from turn off to low power operation v in = v out = 12v ltc4365 ltc4365-1 l l 26 0.3 36 0.7 55 2 ms ms f aul t v ol fault output voltage low i fault = 500a l 0.15 0.4 v i fault fault leakage current fault = 5v, v in = 34v l 20 na note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. all currents into pins are positive; all voltages are referenced to gnd unless otherwise noted. note 3. these pins can be tied to voltages below C0.3v through a resistor that limits the current below 1ma. note 4. the gate pin is referenced to v out and does not exceed 44v for the entire operating range. e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 2.5v to 34v, unless otherwise noted. (note 2) ltc 4365 4365fa
5 for more information www.linear.com/ltc4365 typical p er f or m ance c harac t eris t ics v out operating current vs temperature v out shutdown current vs temperature v out current vs reverse v in v in operating current vs temperature v in shutdown current vs v in v in current vs v in (C40 to 60v) gate current vs gate drive gate drive vs v in gate drive vs temperature temperature (c) ?50 0 i vin (a) 20 40 60 80 0 50 100 4365 g01 100 ?25 25 75 125 shdn = 2.5v v in = 12v v in = 34v v out = v in v in = 2.5v v in (v) 0 0 i vin (a) 5 10 15 25 20 10 20 3530 4365 g02 30 5 15 25 v in = v out shdn = 0v 25c ?45c 125c 70c v in (v) ?50 ?1600 i vin (a) ?1200 ?800 ?400 0 0 50 75 4365 g03 400 ?25 25 shdn = uv = 0v 25c 25c ?45c 125c temperature (c) ?50 0 i vout (a) 40 80 120 160 0 10075 125 4365 g04 200 ?25 25 50 shdn = 2.5v v out = 34v v out = 12v v out = 2.5v v in = v out temperature (c) ?50 0 i vout (a) 5 10 15 0 25 75 100 125 4365 g05 20 ?25 50 shdn = 0v v out = 34v v out = 12v v out = 2.5v v in = v out v in (v) 0 i vout (a) 5 10 15 20 0 ?10 ?30 ?40 ?50 4365 g06 25 ?20 ?45c 25c 125c v out = 0v v in (v) 0 ?v gate (v) 2 4 6 8 10 0 5 15 20 35 25 30 4365 g07 12 10 v out = 0v v out = v in t = 25c i gate = ?1a temperature (c) ?50 0 ?v gate (v) 2 4 6 8 0 50 100 4365 g08 10 ?25 25 75 125 v in = v out = 12v v in = v out = 34v i gate = ?1a v in = v out = 2.5v ?v gate (v) 0 0 i gate(up) (a) ?5 ?10 ?15 ?20 2 6 10 4365 g09 ?25 4 8 v in = v out = 12v 125c 25c ?45c ltc 4365 4365fa
6 for more information www.linear.com/ltc4365 uv/ov propagation delay vs overdrive recovery delay time vs temperature ltc4365 recovery delay time vs v in ov threshold vs temperature uv/ov leakage vs temperature uv threshold vs temperature typical p er f or m ance c harac t eris t ics temperature (c) ?50 492.5 v uv (mv) 495.0 497.5 500.0 502.5 505.0 0 50 100 4365 g10 507.5 ?25 25 75 125 v in = v out = 12v temperature (c) ?50 492.5 v ov (mv) 495.0 497.5 500.0 502.5 505.0 0 50 100 4365 g11 507.5 ?25 25 75 125 v in = v out = 12v temperature (c) ?75 0 i leak (na) 0.25 0.50 0.75 4365 g12 1.00 ?25 25 75 175 125 v uv/ov = 0.5v v in = 12v uv ov overdrive (mv) 1 0 t fault (s) 8 4 12 16 4365 g13 20 10 100 1000 v in = v out = 12v t = 25c temperature (c) ?50 0 t recovery (ms) 10 20 30 40 50 0 50 100 4365 g14 ?25 25 75 125 v in = 34v v in = 12v v in = 2.5v v in (v) 0 0 t recovery (ms) 10 20 30 40 50 10 20 35 4365 g15 5 15 3025 125c 25c ?45c 4365 g16 2.5ms/div gate v out v in 10f, 1k load on v out 60v dual nch mosfet 1v/div 20v/div gnd gnd 4365 g17 250s/div v out gate 100f, 12 load on v out 60v si9945 dual nch mosfet v in = 12v shdn 5v/div 3v/div gnd gnd 4365 g18 250s/div v out shdn gate 100f, 12 load on v out 60v si9945 dual nch mosfet 5v/div 3v/div gnd gnd ltc4365 ac blocking turn-on timing turn-off timing ltc 4365 4365fa
7 for more information www.linear.com/ltc4365 p in func t ions exposed pad: connect to device ground. fault : fault indication output. this high voltage open drain output is pulled low if uv is below its monitor threshold, if ov is above its monitor threshold, if shdn is low, or if v in has not risen above v in(uvlo) . gate: gate drive output for external n-channel mosfets. an internal charge pump provides 20 a of pull-up current and up to 9.8 v of enhancement to the gate of an external n-channel mosfet. when turned off, gate is pulled just below the lower of v in or v out . when v in goes negative, gate is automati- cally connected to v in . gnd: device ground. ov: overvoltage comparator input. connect this pin to an external resistive divider to set the desired v in overvoltage fault threshold. input to an accurate, fast (1 s) compara- tor with a 0.5 v rising threshold and 25 mv of hysteresis. when ov rises above its threshold, a 50 ma current sink pulls down on the gate output. when ov falls back below 0.475v, and after a 36 ms recovery delay waiting period (1ms for ltc4365-1), the gate charge pump is enabled. the low leakage current of the ov input allows the use of large valued resistors for the external resistive divider. connect to gnd if unused. shdn : shutdown control input. shdn high enables the gate charge pump which in turn enhances the gate of an external n- channel mosfet. a low on shdn generates a pull down on the gate output with a 90 a current sink and places the ltc4365 in low current mode (10a ). if unused, connect to v in . if v in goes below ground, or if v in rings to 60v, use a current limiting resistor of at least 100k. uv: undervoltage comparator input. connect this pin to an external resistive divider to set the desired v in undervoltage fault threshold. input to an accurate, fast (1 s) compara- tor with a 0.5 v falling threshold and 25 mv of hysteresis. when uv falls below its threshold, a 50 ma current sink pulls down on the gate output. when uv rises back above 0.525v, and after a 36 ms recovery delay waiting period (1ms for ltc4365-1), the gate charge pump is enabled. the low leakage current of the uv input allows the use of large valued resistors for the external resistive divider. if unused, connect to v in . while connected to v in , if v in goes below ground, or if v in rings to 60 v, use a current limiting resistor of at least 100k. v in : power supply input. maximum protection range: C40v to 60v. operating range: 2.5v to 34v. v out : output voltage sense input. this pin senses the volt - age at the output side of the external n-channel mosfet. the gate charge pump voltage is referenced to v out . it is used as the charge pump input when v out is greater than approximately 6.5v. ltc 4365 4365fa
8 for more information www.linear.com/ltc4365 b lock diagra m v in ?40v to 60v 5v internal supply 6.5v internal supply ldo 2.2v uvlo 0.5v gnd 25mv hysteresis 4365 bd i gate reverse protection closes switch when v in is negative enable gate pulldown fault off turn off 50ma 90a shdn shdn gate charge pump f = 400khz v out uv ov ? + delay timers logic ? + ? + fault gate many of todays electronic systems get their power from external sources such as wall wart adapters, batteries and custom power supplies. a typical supply arrangement for a portable product is shown by the operational diagram in figure 1. power is supplied by an ac adaptor or, if the plug is withdrawn, by a removable battery. trouble arises when any of the following occurs: ? the battery is installed backwards ? an ac adaptor of opposite polarity is attached ? an ac adaptor of excessive voltage is attached ? the battery is discharged below a safe level this can lead to supply voltages that are too high, too low, or even negative. if these power sources are applied directly to the electronic systems, the systems could be subject to damage. the ltc4365 is an input voltage fault protection n- channel mosfet controller. the part isolates an input supply from its load to protect the load from unexpected supply voltage conditions, while providing a low loss path for qualified power. to protect electronic systems from improperly connected power supplies, system designers will often add discrete diodes, transistors and high voltage comparators. the high voltage comparators enable system power only if the input supply falls within a desired voltage window. a schottky diode or p-channel mosfet typically added in series with the supply protects against reverse supply connections. the ltc4365 provides accurate overvoltage and under - voltage comparators to ensure that power is applied to o pera t ion ltc 4365 4365fa
9 for more information www.linear.com/ltc4365 o pera t ion the system only if the input supply meets the user select- able voltage window. reverse supply protection circuits automatically isolate the load from negative input voltages. during normal operation, a high voltage charge pump a pplica t ions i n f or m a t ion the ltc4365 is an n-channel mosfet controller that protects a load from faulty supply connections. a basic application circuit using the ltc4365 is shown in figure 2 the circuit provides a low loss connection from v in to v out as long as the voltage at v in is between 3.5 v and v in uv ov shdn ov = 18v uv = 3.5v 4365 f02 v out fault gate v in 12v nominal v out 3.5v to 18v si4946 60v dual gnd ltc4365 r5 100k c out 100f r3 1820k r2 243k r1 59k + m1 m2 figure 1. operational diagram common to many portable products 18v. voltages at v in outside of the 3.5 v to 18 v range are prevented from getting to the load and can be as high as 60v and as low as C40 v. the circuit of figure 2 protects against negative voltages at v in as shown. no other external components are needed. during normal operation, the ltc4365 provides up to 9.8v of gate enhancement to the external back-to-back n-channel mosfets. this turns on the mosfet, thus connecting the load at v out to the supply at v in . gate drive the ltc4365 turns on the external n-channel mosfets by driving the gate pin above v out . the voltage difference between the gate and v out pins ( gate drive) is a function of v in and v out . enhances the gate of external n-channel power mosfets. power consumption is 10 a during shutdown and 125 a while operating. the ltc4365 integrates all these func - tions in tiny tsot-23 and 3mm 2mm dfn packages. v in uv ov shdn 2.5v to 34v operating range 4365 f01 v out fault gate gnd ltc4365 r5 r3 battery ?40v to 60v protection range ac adaptor input ov, uv protection thresholds set to satisfy load circuit r2 r1 m1 m2 load circuit + ? figure 2. ltc4365 protects load from C40v to 60v v in faults ltc 4365 4365fa
10 for more information www.linear.com/ltc4365 overvoltage and undervoltage protection the ltc4365 provides two accurate comparators to moni- tor for overvoltage ( ov) and undervoltage ( uv) conditions at v in . if the input supply rises above the user adjustable ov threshold, the gate of the external mosfet is quickly turned off, thus disconnecting the load from the input. similarly, if the input supply falls below the user adjust - able uv threshold, the gate of the external mosfet also is quickly turned off. figure 4 shows a uv/ov application for an input supply of 12v. figure 3. gate drive (gate C v out ) vs v out a pplica t ions i n f or m a t ion figure 3 highlights the dependence of the gate drive on v in and v out . when system power is first turned on (shdn low to high, v out = 0 v), gate drive is at a maximum for all values of v in . this helps prevent start-up problems into heavy loads by ensuring that there is enough gate drive to support the load. as v out ramps up from 0 v, the absolute value of the gate voltage remains fixed until v out is greater than the lower of (v in C1 v) or 6 v. once v out crosses this threshold, gate drive begins to increase up to a maximum of 9.8v (for v in 12 v). the curves of figure 3 were taken with a gate load of C1 a. if there were no load on gate, the gate drive for each v in would be slightly higher. note that when v in is at the lower end of the operating range, the external n-channel mosfet must be selected with a corresponding lower threshold voltage. v in 12v uv th = 3.5v ov th = 18v 4365 f04 discharge gate with 50ma sink ltc4365 ov comparator uv comparator r3 1820k uv 0.5v 0.5v ov r2 243k r1 59k ? + 25mv ? + 25mv figure 4. uv, ov comparators monitor 12v supply the external resistive divider allows the user to select an input supply range that is compatible with the load at v out . furthermore, the uv and ov inputs have very low leakage currents (typically < 1 na at 100 c), allowing for large values in the external resistive divider. in the applica - tion of figure 4, the load is connected to the supply only if v in lies between 3.5 v and 18 v. in the event that v in goes above 18 v or below 3.5v , the gate of the external n- channel mosfet is immediately discharged with a 50 ma current sink, thus isolating the load from the supply. table 1 lists some external mosfets compatible with different v in supply voltages. table 1. dual mosfets for various supply ranges v in mosfet v th(max) v gs(max) v ds(max) 2.5v sib914 0.8v 5v 8v 3.3v si5920 1.0v 5v 8v 5v si7940 1.5v 8v 12v 30v si4214 3.0v 20v 30v 60v si9945 3.0v 20v 60v v out (v) 0 0 ?v gate (v) 2 4 6 10 8 12 9 15 4365 f03 3 6 12 v in = 30v v in = 12v v in = 5v v in = 3.3v v in = 2.5v t = 25c i gate = ?1a ltc 4365 4365fa
11 for more information www.linear.com/ltc4365 figure 5 shows the timing associated with the uv pin. once a uv fault propagates through the uv comparator (t fault ), the fault output is asserted low and a 50ma current sink discharges the gate pin. as v out falls, the gate pin tracks v out . a pplica t ions i n f or m a t ion figure 6 shows the timing associated with the ov pin. once an ov fault propagates through the ov comparator (t fault ), the fault output is asserted low and a 50ma current sink discharges the gate pin. as v out falls, the gate pin tracks v out . procedure for selecting uv/ ov external resistor values the following 3- step procedure helps select the resistor values for the resistive divider of figure 4. this procedure minimizes uv and ov offset errors caused by leakage currents at the respective pins. 1. choose maximum tolerable offset at the uv pin, v os(uv) . divide by the worst case leakage current at the uv pin, i uv (10 na). set the sum of r1 + r2 equal to v os(uv) divided by 10 na. note that due to the presence of r3, the actual offset at uv will be slightly lower: r1 + r2 = v os(uv) i uv 2. select the desired v in uv trip threshold, uv th . find the value of r3: r3 = v os(uv) i uv ? uv th C 0.5v 0.5v ? ? ? ? ? ? 3. select the desired v in ov trip threshold, ov th . find the values of r1 and r2: r1 = v os(uv) i uv ? ? ? ? ? ? + r3 ov th ? 0.5v r2 = v os(uv) i uv C r1 the example of figure 4 uses standard 1% resistor values. the following parameters were selected: v os(uv) = 3mv i uv = 10na uv th = 3.5v ov th = 18v 4365 f05 fault gate t fault t gate(fast) v uv v uv + v uvhyst t fault t recovery external n-channel mosfet turns off uv 4365 f06 fault gate t fault t gate(fast) v ov v ov ? v ovhyst t fault t recovery external n-channel mosfet turns off ov figure 5. uv timing (ov < (v ov C v ovhyst ), shdn > 1.2v) figure 6. ov timing (uv > (v uv + v uvhyst ), shdn > 1.2v) when both the uv and ov faults are removed, the external mosfet is not immediately turned on. the input supply must remain within the user selected power good window for at least 36ms (t recovery ) before the load is again connected to the supply. this recovery timeout period filters noise ( including line noise) at the input supply and prevents chattering of power at the load. for applications that require faster turn-on after a fault, the ltc4365-1 provides a 1ms recovery timeout period. ltc 4365 4365fa
12 for more information www.linear.com/ltc4365 a pplica t ions i n f or m a t ion the resistor values can then be solved: 1. r1 + r2 = 3mv 10na = 300k 2. r3 = 2 ? 3mv 10na ? (3.5v C 0.5v) = 1.8m the closest 1% value: r3 = 1.82m: 3. r1 = 300k + 1.82m 2 ? 18v = 58.9k the closest 1% value: r1 = 59k: r2 = 300k C 59k = 241k the closest 1% value: r2 = 243k therefore: ov = 17.93v, uv = 3.51v. reverse v in protection the ltc4365s rugged and hot-swappable v in input helps protect the more sensitive circuits at the output load. if the input supply is plugged in backwards, or a negative supply is inadvertently connected, the ltc4365 prevents this negative voltage from passing to the output load. the ltc4365 employs a novel, high speed reverse supply voltage monitor. when the negative v in voltage is detected, an internal switch connects the gates of the external back- to-back n-channel mosfets to the negative input supply. as shown in figure 7, external back-to-back n-channel mosfets are required for reverse supply protection. when v in goes negative, the reverse v in comparator closes the internal switch, which in turn connects the gates of the external mosfets to the negative v in voltage. the body diode ( d1) of m1 turns on, but the body diode ( d2) of m2 remains in reverse blocking mode. this means that the common source connection of m1 and m2 remains about a diode drop higher than v in . since the gate voltage of m 2 is shorted to v in , m2 will be turned off and no cur- rent can flow from v in to the load at v out . note that the voltage rating of m2 must withstand the reverse voltage excursion at v in . figure 8 illustrates the waveforms that result when v in is hot plugged to C20 v. v in , gate and v out start out at ground just before the connection is made. due to the parasitic inductance of the v in and gate connections, the voltage at the v in and gate pins ring significantly below C20v. therefore, a 40 v n-channel mosfet was selected to survive the overshoot. the speed of the ltc4365 reverse protection circuits is evident by how closely the gate pin follows v in during the negative transients. the two waveforms are almost indistinguishable on the scale shown. the trace at v out , on the other hand, does not respond to the negative voltage at v in , demonstrating the desired reverse supply protection. the waveforms of figure 8 were captured using a 40 v dual n-channel mosfet, a 10f ceramic output capacitor and no load current on v out . figure 7. reverse v in protection circuits v in 4365 f07 v out gate v in = ?40v reverse v in comparator closes switch when v in is negative gnd ltc4365 m1 d1 d2 m2 + ? + to load c out figure 8. hot swapping v in to C20v ?20v 5v/div gnd 4365 f07 500ns/div gate v out v in ltc 4365 4365fa
13 for more information www.linear.com/ltc4365 recovery timer the ltc4365 has a recovery delay timer that filters noise at v in and helps prevent chatter at v out . after either an ov or uv fault has occurred, the input supply must return to the desired operating voltage window for at least 36ms (t recovery ) in order to turn the external mosfet back on as illustrated in figure 5 and figure 6. for applications that require faster turn-on after a fault, the ltc4365-1 provides a 1ms recovery timeout period. going out of and then back into fault in less than t recovery will keep the mosfet off continuously. similarly, coming out of shutdown (shdn low to high) triggers an 800s start-up delay timer (see figure 11). the recovery timer is also active while the part is power - ing up . the recovery timer starts once v in rises above v in(uvlo) and v in lies within the user selectable uv/ov power good window. see figure 9. gentle shutdown the shdn input turns off the external mosfets in a gentle, controlled manner. when shdn is asserted low, a 90a current sink slowly begins to turn off the external mosfets . once the voltage at the gate pin falls below the voltage at the v out pin, the current sink is throttled back and a feedback loop takes over. this loop forces the gate voltage to track v out , thus keeping the external mosfets off as v out decays. note that when v out < 4.5 v, the gate pin is pulled to within 400mv of ground. gentle gate turn off reduces load current slew rates and mitigates voltage spikes due to parasitic inductances. to further decrease gate pin slew rate, place a capacitor across the gate and source terminals of the external mos - fets. the waveforms of figure 10 were captured using the si4214 dual n-channel mosfets, and a 2 a load with 100f output capacitor. a pplica t ions i n f or m a t ion 4365 f09 gate mosfet off mosfet on v in v in(uvlo) t recovery figure 9. recovery timing during power-on (ov = gnd, uv = shdn = v in ) figure 10. gentle shutdown: gate tracks v out as v out decays gate v out t gate(slow) gate = v out t start t shdn(f) ?v gate shdn 4365 f11 fault figure 11. gentle shutdown timing fault status the fault high voltage open drain output is driven low if shdn is asserted low, if v in is outside the desired uv/ov voltage window, or if v in has not risen above v in(uvlo) . figure 5, figure 6 and figure 11 show the fault output timing. 5v/div 4365 f10 100s/div gate v out shdn v in = 12v t = 25c gnd select between tw o input supplies with the part in shutdown, the v in and v out pins can be driven by separate power supplies. the ltc4365 then automatically drives the gate pin just below the lower of ltc 4365 4365fa
14 for more information www.linear.com/ltc4365 the two supplies, thus turning off the external back- to- back mosfets. the application of figure 12 uses two ltc4365s to select between two power supplies. care should be taken to ensure that only one of the two ltc4365s is enabled at any given time. a pplica t ions i n f or m a t ion figure 12. selecting one of tw o supplies v in v2 shdn 4365 f12 v out gate ltc4365 v in v1 sel 0 1 out v1 v2 out m2 m1 m2 m1 sel shdn v out gate ltc4365 limiting inrush current during turn-on the ltc4365 turns on the external n-channel mosfet with a 20 a current source. the maximum slew rate at the gate pin can be reduced by adding a capacitor on the gate pin: slew rate = 20a c gate since the mosfet acts like a source follower, the slew rate at v out equals the slew rate at gate. therefore, inrush current is given by: i inrush = c out c gate ? 20a for example, a 1 a inrush current to a 330 f output capacitance requires a gate capacitance of: c gate = 20a ? c out i inrush c gate = 20a ? 330f 1a = 6.6nf the 6.8 nf c gate capacitor in the application circuit of figure 14 limits the inrush current to approximately 1a. r gate makes sure that c gate does not affect the fast gate turn off characteristics during uv/ov faults, or during reverse v in connection. r4a and r4b help prevent high frequency oscillations with the external n- channel mosfet and related board parasitics. v in uv ov shdn ov = 30v 4365 f13 v out fault gate v in 24v si7120dn 60v v out gnd ltc4365 r2 2370k r1 40.2k c out 100f + r5 100k figure 13. small footprint single mosfet application protects against 60v 4365 f14 v in v in v out r4b 10 r4a 10 c out 330f v out gate ltc4365 r gate 5.1k c gate 6.8nf + m2 m1 figure 14. limiting inrush current with c gate single mosfet application when reverse v in protection is not needed, only a single external n-channel mosfet is necessary. the applica- tion cir cuit of figure 13 connects the load to v in when v in is less than 30 v, and uses the minimal set of external components. ltc 4365 4365fa
15 for more information www.linear.com/ltc4365 a pplica t ions i n f or m a t ion transients during ov fault the circuit of figure 15 was used to display transients during an overvoltage condition. the nominal input supply is 24 v and it has an overvoltage threshold of 30 v. the parasitic inductance is that of a 1 foot wire ( roughly 300 nh). figure 16 shows the waveforms during an overvoltage condition at v in . these transients depend on the parasitic inductance and resistance of the wire along with the ca- pacitance at the v in node. d1 is an optional power clamp ( tvs , tranzorb) recommended for applications where the dc input voltage can exceed 24 v and with large v in parasitic inductance. no clamp was used to capture the waveforms of figure 16. in order to maintain reverse sup - ply protection, d1 must be a bi-directional clamp rated for at least 225w peak pulse power dissipation. v in uv ov shdn ov = 30v 4365 f15 v out fault gate m1 m2 v in 24v si9945 60v 12 inch wire length v out gnd ltc4365 r2 2370k r1 40.2k r3 100k c out 100f + c in 1000f d1 optional + 9 2a/div gnd gnd 0a 20v/div 20v/div 4365 f16 250ns/div gate v out v in i in gate v out figure 15. ov fault with large v in inductance figure 16. transients during ov fault when no tranzorb ( tvs ) is used ltc 4365 4365fa
16 for more information www.linear.com/ltc4365 r egulator a pplications hysteretic regulator built-in hysteresis and the availability of both inverting and noninverting control inputs ( ov and uv) facilitate the design of hysteretic regulators. figure 17 shows how the ltc4365-1 can protect a load from ov transients, while regulating the output voltage at a user-defined level. when the output voltage reaches its ov limit, the ltc4365-1 turns off the external mosfets. the load current then discharges the output capacitance until ov falls below the hysteresis voltage. the external mosfets are turned back on after a 1 ms delay. figure 18 shows the waveforms for the circuit of figure 17. note that the duration, magnitude and duty cycle of the v in glitch must not exceed the soa rating of the external mosfets. solar charger figure 19 shows a series regulator for a solar charger. the ltc4365-1 connects the solar charger to the battery when the battery voltage falls below 13.9v ( after a 1ms delay). conversely, when the battery reaches 14.6 v, the ltc4365-1 immediately (2s) opens the charging path. regulation of the battery voltage is achieved by connect- ing a resistive divider from the battery to the accurate ov comparator input (with 5% hysteresis). the fast rising response of the ov comparator prevents the batter y voltage from rising above the user-selected threshold. a pplica t ions i n f or m a t ion figure 17. hysteretic regulation of v out during ov transients figure 18. v out regulates at 16v when v in glitches above desired level v in uv ov shdn 4365 f17 v out fault gate v in 12v si4946 dual nch optional snubber v out gnd ltc4365-1 r5 510k c load 47f c ov 220pf + r load 100 r2 1820k r1 59k 1f r7 1 4365 f18 2.5ms/div 5v/div gnd v out v in v in 4365 f19 v out gate uv shdn 1/2 of si4214 1/2 of si4214 gnd ltc4365-1 ov m1 d1 d4 b130 d2 m2 + to load c batt 100f c byp 100nf 15w solar panel r2 3.24m r1 115k 14.6v off 13.9v on c ov 220pf 12v, 8ah gelcell figure 19. series hysteretic solar charger with reverse-battery and solar panel protection ltc 4365 4365fa
17 for more information www.linear.com/ltc4365 a pplica t ions i n f or m a t ion note that during initial start-up, the ltc4365-1 will not turn on the external mosfets until a battery is first con- nected to the v in pin. to begin operation, v in must initially rise above the 2.2 v uvlo lockout voltage. connecting the battery ensures that the ltc4365-1 comes out of uvlo. 12v application with 150v transient protection figure 20 shows a 12 v application that withstands input supply transients up to 150v. when the input voltage ex - ceeds 17.9 v, the ov resistive divider turns off the external mosfets. as v in rises to 150 v, the gate of transistor m1 remains in the off condition, thus preventing conduction from v in to v out . note that m1 must have an operating range above 150v. resistor r6 and diode d3 clamp the ltc4365 supply volt - age to 50 v. to prevent r6 from interfering with reverse operation, the recommended value is 1 k or less. note that the power handling capability of r6 must be considered in order to avoid overheating during transients. d3 is shown as a bidirectional clamp in order to achieve reverse-polarity protection at v in . m2 is also required in order to protect v out from negative voltages at v in and should have an operating range beyond the breakdown of d3. if reverse protection is not desired remove m2 and connect the source of m1 directly to v out . mosfet selection to protect against a negative voltage at v in , the external n-channel mosfets must be configured in a back-to- back arrangement. dual n-channel packages are thus the best choice. the mosfet is selected based on its power handling capability, drain and gate breakdown voltages, and threshold voltage. the drain to source breakdown voltage must be higher than the maximum voltage expected between v in and v out . note that if an application generates high energy transients during normal operation or during hot swap?, the external mosfet must be able to withstand this transient voltage. due to the high impedance nature of the charge pump that drives the gate pin, the total leakage on the gate pin must be kept low. the gate drive curves of figure 2 were measured with a 1 a load on the gate pin. therefore, the leakage on the gate pin must be no greater than 1 a in order to match the curves of figure 2. higher leakage currents will result in lower gate drive. the dual n-channel mosfets shown in table 1 all have a maximum gate leakage current of 100na. additionally, table 1 lists representative mosfets that would work at different values of v in . layout considerations the trace length between the v in pin and the drain of the external mosfet should be minimized, as well as the trace length between the gate pin of the ltc4365 and the gates of the external mosfets. place the bypass capacitors at v out as close as possible to the external mosfet. use high frequency ceramic capacitors in addition to bulk capacitors to mitigate hot swap ringing. place the high frequency capacitors closest to the mosfet. note that bulk capacitors mitigate ringing by virtue of their esr. ceramic capacitors have low esr and can thus ring near their resonant frequency. figure 20. 12v application protected from 150v transients v in uv ov shdn ov = 17.9v d3: smaj43ca bi-directional 4365 f20 v out fault gate m1 m2 v in 12v fdb33n25 v out gnd ltc4365 r3 510k d3 r2 2050k r1 59k r6 1k ltc 4365 4365fa
18 for more information www.linear.com/ltc4365 p ackage descrip t ion ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702 rev b) 1.50 ? 1.75 (note 4) 2.80 bsc 0.22 ? 0.36 8 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) ts8 tsot-23 0710 rev a 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.40 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637 rev a) 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.15 0.05 (2 sides) 3.00 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0 ? 0.05 (ddb8) dfn 0905 rev b 0.25 0.05 2.20 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.25 0.05 0.50 bsc pin 1 r = 0.20 or 0.25 45 chamfer 0.50 bsc please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. ltc 4365 4365fa
19 for more information www.linear.com/ltc4365 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 09/13 added ltc4365-1 information multiple operation section: rewritten with new figure 1 8, 9 table 1: mosfet for 30v changed to si4214 from si4230 10 figure 13: inserted r5, 100k resistor to shdn pin 14 added "regulator applications" with three subsections and figures 17 to 20 16, 17 updated typical application 20 ltc 4365 4365fa
20 for more information www.linear.com/ltc4365 ? linear technology corporation 2013 lt 0913 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc4365 r ela t e d p ar t s typical a pplica t ion ltc4365 protects step down regulator from C30v to 30v v in faults part number description comments lt4363 surge stopper overvoltage/overcurrent protection regulator wide operating range: 4v to 80v, reverse protection to C60v, adjustable output clamp voltage ltc4364 surge stopper with ideal diode 4v to 80v operation, C40v reverse input, C20v reverse output ltc4366 floating surge stopper 9v to >500v operation, 8-pin tsot and 3mm 2mm dfn packages ltc4361 overvoltage/overcurrent protection controllers 5.8v overvoltage threshold, 85v absolute maximum ltc2909 triple/dual inputs uv/ov negative monitor pin selectable input polarity allows negative and ov monitoring ltc2912/ltc2913 single/dual uv/ov voltage monitor ads uv and ov trip values, 1.5% threshold accuracy ltc2914 quad uv/ov monitor for positive and negative supplies ltc2955 pushbutton on/off controller automatic turn-on, 1.5v to 36v input, 36v pb input lt4256 positive 48v hot swap controller with open-circuit detect foldback current limiting, open-cir cuit and overcurrent fault output, up to 80v supply ltc4260 positive high v oltage hot swap controller with adc and i 2 c wide operating range 8.5v to 80v ltc4352 ideal mosfet oring diode external n-channel mosfets replace oring diodes, 0v to 18v ltc4354 negative voltage diode-or controller controls tw o n-channel mosfets, 1.2s turn-off, C80v operation ltc4355 positive voltage diode-or controller controls tw o n-channel mosfets, 0.4s turn -off, 80v operation lt 1913 step-down switching regulator 3.6v to 25v input, 3.5a maximum current, 200khz to 2.4mhz v in uv ov shdn ov = 18v uv = 3.5v 4365 ta02 v out fault gate si4214 30v dual n-channel v out protected from ?30v to 30v v in 12v nominal v out gnd ltc4365 510k 10f 1820k 243k 59k sw fb v c pg rt v in bd output 5v 3.5a 0.47f 47f 100k 15k 63.4k 4.7h 536k gnd lt1913 run/ss boost sync 680pf ltc 4365 4365fa

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